1. Field of the Invention
The present invention relates to semiconductor packaging, and more particularly to a semiconductor module.
2. Description of the Related Art
In the field of electronic systems, there is a continuous need to increase performance and reduce size. This is largely achieved by improving semiconductor wafer manufacturing and semiconductor packaging technologies. Wafer manufacturing involves simultaneously fabricating numerous semiconductor chips as a batch on a silicon wafer using various etching, doping and depositing steps. After the wafer is complete, the chips are separated from one another and packaged.
Wafer manufacturing strives to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality. Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices. Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future. However, significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to semiconductor packaging as a means to fulfill the relentless demands for enhanced system performance.
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. Traditionally, a single chip is individually housed in a single-chip package that is connected to other single-chip packages through a printed circuit board (or motherboard) which supplies power to the chips and provides signal routing among the chips. The single-chip package has connection media that is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate).
Several connection techniques are widely used for connecting the chip pads and the connection media. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding. Wire bonding is by far the most common. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface. Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Many variations exist on these basic methods.
A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used. While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. In addition, an adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. Thus, none of these conventional connection techniques are entirely satisfactory.
Conventional single-chip packages typically have an area (or footprint) that is many times larger than the area of the chip, causing the printed circuit board to have excessively large area relative to the chips. However, as chip speeds increase, it becomes critical to position the chips close together since excessive signal transmission distance deteriorates signal integrity and propagation times. Other considerations such as manufacturing cost, reliability, heat transfer, moisture resistance, mounting and interconnect standardization, testability, and quality control have also become focal points of chip packaging.
Single-chip packages such as ball grid arrays (BGA) and chip scale packages (CSP) have been recently developed to address these considerations. Although these packages provide certain advantages, further size reduction and performance enhancement with these packages has been difficult to obtain due to physical dimension, design and manufacturing constraints.
Multichip modules (MCM) or-hybrid modules that package multiple chips on a common platform are an alternative to single-chip packages. These modules aim to achieve higher packaging density (lower volume and mass per chip), better signal integrity and reasonable manufacturing cost. Conventional multichip modules are essentially two-dimensional structures with multiple chips connected to a planar interconnection substrate which contains traces to supply power and signal transmission. Co-fired ceramic substrates have given way to organic-based substrates due to performance and cost advantages. However, since multichip modules utilize a planar interconnection substrate as the base, their effectiveness in packaging density is limited. For instance, a substrate transmission line that is 25 microns wide, 5 microns high and 10 millimeters long creates high line resistance and signal delays, which necessitates complex wiring rules in order to provide acceptable signal transmission distances and reasonable propagation delays.
Therefore, in order to create higher density packages, reduce area requirements and shorten signal transmission distances, three-dimensional packages with two, three or more vertically stacked chips are an emerging trend. Three-dimensional packages are particularly suitable for the electronic systems such as supercomputers and large cache memory devices which require high operating speed and high capacity in very limited space.
Three-dimensional packages generally follow two approaches. In one approach, individual chips are packaged in conventional single-chip packages and then the single-chip packages are vertically stacked and interconnected to one another. Single-chip packages stacked this way include thin small-outline packages (TSOP), ball grid arrays (BGA) and tape chip packages (TCP), and chip connections within the single-chip packages include wire bonding, TAB and flip-chip bonding. In another approach, leads are connected to the chips, and then the exposed leaded chips are vertically stacked and interconnected to one another. Most three-dimensional packages involve peripheral interconnection, but some provide area array interconnection. Numerous three-dimensional packages are reported in the literature.
U.S. Pat. Nos. 5,484,959, 5,514,907, 5,625,221 and 5,744,827 disclose three-dimensional packages in which stacked single-chip packages have large footprints that require large amounts of space. The single-chip packages also have long extended leads and associated wire bonds that limit electrical performance.
U.S. Pat. Nos. 5,854,507 and 6,072,233 disclose three-dimensional packages with stacked single-chip packages in which solder balls provide the primary vertical interconnects. The solder balls require large amounts of space.
U.S. Pat. No. 5,394,303 discloses a three-dimensional package in which the stacked single-chip packages include a flexible film with wiring layers wrapped around the chip. The flexible film is relatively difficult to wrap and bending the wiring layers causes low yields.
U.S. Pat. Nos. 4,996,583, 5,138,438 and 5,910,685 disclose three-dimensional packages in which TAB leads are connected to and extend beyond the peripheries of the chips, the exposed chips are stacked together and the TAB leads are connected together. The TAB leads for different chips have different shapes and lengths which complicates manufacturing. Furthermore, the TAB leads are interconnected by applying thermocompression, which also complicates manufacturing.
U.S. Pat. Nos. 4,706,166 and 5,104,820 disclose three-dimensional packages in which chips are formed with leads that extend to the sidewalls, the exposed chips are stacked together, and then thin film routing lines are deposited on the sidewalls to interconnect the leads. The wafer process must be modified, and aligning the sidewalls and forming the routing lines on the leads is difficult.
U.S. Pat Nos. 4,897,708 and 4,954,875 disclose three-dimensional packages composed of wafers rather than individual chips. Cone-shaped vias are formed in the wafers, electrically conductive material is filled in the vias which contacts the pads on the wafers, and the wafers are stacked such that the electrically conductive material in the vias provides vertical interconnects between the pads. The wafer stacks are difficult to separate for repairs and too large for many applications.
Another drawback with many conventional three-dimensional packages is that the vertical interconnects lack the flexibility to accommodate thickness variations of the stacked assemblies. For instance, chip thickness may vary by 20 microns or more even after back-side wafer polishing attempts to planarize the wafer. As a result, vertical interconnects with fixed heights cannot adequately accommodate these thickness variations, and suffer from disoriented, cracked and open connections, high mechanical stress and reliability problems.
In summary, conventional three-dimensional packages suffer from numerous deficiencies including large area requirements, inflexible vertical interconnects, limited electrical performance, poor structural strength and low reliability. Moreover, conventional three-dimensional packages are often manufactured by complicated processes that are impractical for volume production, and too difficult and costly to develop.
In view of the various development stages and limitations in currently available three-dimensional packages, there is a need for a semiconductor module that is cost-effective, reliable, manufacturable, and provides excellent mechanical and electrical performance.
An object of the present invention is to provide a semiconductor module that provides a low cost, high performance, high reliability package. Another object of the present invention is to provide a convenient, cost-effective method of making a semiconductor module.
In accordance with one aspect of the invention, a semiconductor module includes a first semiconductor chip assembly, a second semiconductor chip assembly, an encapsulant base and an electrical interconnect. The first assembly includes a first semiconductor chip, a first conductive trace and a first connection joint, the first chip includes a first conductive pad, the first trace extends within and outside a periphery of the first chip, and the first connection joint contacts and electrically connects the first trace and the first pad. The second assembly includes a second semiconductor chip, a second conductive trace and a second connection joint, the second chip includes a second conductive pad, the second trace extends within and outside a periphery of the second chip, and the second connection joint contacts and electrically connects the second trace and the second pad. The encapsulant base is disposed between and in contact with the first and second chips and the first and second traces. The electrical interconnect contacts the first and second traces in a through-hole that extends through the encapsulant base and is located outside the peripheries of the chips, thereby electrically connecting the first and second traces.
Preferably, the first pad faces away from the second chip, the second pad faces away from the first chip, the first trace is a planar metal lead that overlaps the first pad and the second trace is a planar metal lead that overlaps the second pad.
It is also preferred that the encapsulant base is transfer molded plastic and the electrical interconnect is plated metal.
It is also preferred that the module is a dual in-line memory module that is devoid of wire bonds, TAB leads and solder joints.
In accordance with another aspect of the invention, a method of making a semiconductor module includes providing a first semiconductor chip assembly that includes a first semiconductor chip and a first carrier wherein the first chip includes a first conductive pad and the first carrier includes a first conductive trace, providing a second semiconductor chip assembly that includes a second semiconductor chip and a second carrier wherein the second chip includes a second conductive pad and the second carrier includes a second conductive trace, forming an encapsulant base between and in contact with the first and second assemblies, forming a through-hole that extends through the carriers and the encapsulant base and is located outside the peripheries of the first and second chips, forming an electrical interconnect in the through-hole that contacts the first and second traces in the through-hole, and forming first and second connection joints wherein the first connection joint contacts and electrically connects the first trace and the first pad and the second connection joint contacts and electrically connects the second trace and the second pad.
Preferably, the encapsulant base is formed by transfer molding and contacts the first and second chips, the through-hole is formed by mechanical drilling, the electrical interconnect is formed by electroless plating followed by electroplating, and the connection joints are formed by electroless plating.
It is also preferred that an attachment joint mechanically attaches the first and second assemblies before the encapsulant base is formed, and the attachment joint is removed after the encapsulant base is formed. For instance, the first carrier can be bent at opposing lateral ends to form a pair of legs that extend across a-thickness of the first chip, the carriers can be positioned so that the legs extend across a thickness of the second chip and contact the second carrier, and then the attachment joint can be formed by welding the legs to the second carrier.
It is also preferred that the steps after providing the first and second assemblies are performed in the sequence set forth.
An advantage of the semiconductor module of the present invention is that it is reliable, cost-effective, easily manufacturable, contains ultra-thin semiconductor chip assemblies in an integrated module, and can be directly mounted on a printed circuit board. Another advantage is that the encapsulant base provides both encapsulation for the chips and mechanical support for the module. Another advantage is that the module can accommodate chips with varying sizes and thickness while maintaining reliable vertical electrical interconnects between the chips.
Another advantage is that the module is well-suited for severe operational conditions due to low stress at the vertical electrical interconnects and short signal paths between the chips. Another advantage is that the module can be manufactured using low temperature processes which reduces stress and improves reliability. A further advantage is that the module can be manufactured using well-controlled processes which can be easily implemented by circuit board, lead frame and tape manufacturers.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.